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│ │ ┌─┐ │ ＴＨＥ │ │ ┌─┐ │
│ └─┘ │ │ │ └─┘ │ │
└─────┘ │ P u b l i c D o m a i n M a n u a l └─────┘ │
┌─────┐ │ ┌─────┐ │
│ ┌─┐ │ │ ｏｆ │ ┌─┐ │ │
│ │ └─┘ │ │ │ └─┘ │
│ └─────┘ E n h a n c e d G r a p h i c C h a r g e r │ └─────┘
│ ┌─────┐ │ ┌─────┐
│ │ ┌─┐ │ │ │ ┌─┐ │
│ └─┘ │ │ (Ver. 0.55) │ └─┘ │ │
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Written by Ａｐｐｌａｕｓｅ
Introduction
Although the 98 series is widely used, it is difficult to obtain a complete manual including EGC. Even when they got their hands on it, there were many mistakes, and many people must have wondered why it didn't work the way they wanted, and I think they must have lost their passion for machine language and felt sad. In general, Japanese manuals are unfriendly, hard to read, and full of errors. Therefore, I would like to announce this EGC manual so that those who have been frustrated or who are about to take on the challenge do not have to re-analyze the hardware themselves.
Taking in routines made by others and mastering them is an art, but it's also fun to control hardware with your own hands using machine language. I would like many people to know that kind of fun.
By using EGC's functions such as 4-plane simultaneous transfer, 4-plane simultaneous operation, dot unit shift, etc., box copy routines, high-speed paint routines, and high-speed pseudo-sprites using half of VRAM as a sprite area can be realized. .
Programmers, please create a PDS that makes the most of EGC based on this manual and entertain many 98 owners.
Please note that this manual is not official and may contain errors. Please contact us if you have noticed. Also, it may not always be the case that the aim of "making it as easy to read as possible" is achieved. Please excuse me for now.
╌╌╌╌╌╌╌╌╌╌╌ § § § Enabling EGC § § § ╌╌╌╌╌╌╌╌╌╌╌╌
As you can see from the fact that EGC is an abbreviation for Enhanced Graphic Charger, it is an extension of GRCG (Graphic Charger). Therefore, to enable EGC, first enable GRCG and then switch to EGC mode. In practice:
EGC_ONPROC
MOVAL, 80H; Enable GRCG. 80H may be C0H.
OUT7CH,AL;
MOVAL,7; make flip-flop changeable
OUT6AH,AL;
MOVAL,5; to EGC mode
OUT6AH,AL;
MOVAL,6; make flip-flop immutable
OUT6AH,AL;
END SUB
There should be no problem even if you do not take the step of making it impossible to change the last flip-flop, but if there is a program that writes to I/O port 6AH by mistake, it is necessary to find out the cause of the abnormality. This is probably because it makes it difficult to do so. Also, even if you don't insert waits, the 9821Ap will still work, so there will be no problem. If MATE contains an EGC for MATE, there is no basis for this.
╌╌╌╌╌╌╌╌╌╌╌╌╌╌╌ § § § EGC registers § § § ╌╌╌╌╌╌╌╌╌╌╌╌╌╌
The EGC has a total of eight 16-bit registers, and the EGC operating mode is specified by setting values in these with the OUT DX and AX instructions.
<<Plane mask register, I/O port 4A0H>>
This register sets whether writing or reading by EGC is enabled or disabled for each plane.
Bit 0 of this register corresponds to plane 0, bit 1 to plane 1, bit 2 to plane 2, and bit 3 to plane 3.
These bits:
If it is 0, the contents of the plane corresponding to the bit are rewritten by writing,
If it is 1, the contents of the corresponding plane remain unchanged. That is, the plane is said to be "masked."
Also, the compare read described later is performed for the planes where the above bit corresponding to each plane is 0.
Bits 4 to 15 are unused in the 16-color display mode out of 4,096 colors, so they are all set to 1.
(In fact, we have actually confirmed that in H98's 256-color display mode out of 16,777,216 colors, bits 4 to 7 correspond to planes 4 to 7. Unfortunately, it is not known whether EGC is valid in the 65,536 color mode of PC9801GS, or whether bits 8 to 15 correspond to planes 8 to 15.)
<<Mode register 0, I/O port 4A2H>>
• Bits 0 to 7 of this register are unused. Set all to 1.
・ With bits 8 to 11, select the plane to read when reading one plane.
Set as a 4-bit number. Namely
bit 11 10 9 8
If 0 0 0 0, then plane 0 is read.
If 0 0 0 1, read plane 1.
If 0 0 1 0, read plane 2.
If 0 0 1 1, read plane 3.
That's how it is.
(This 4-bit
If you set a value between 4 and 7 in , plane 4 to plane 7 are specified.
Whether it will be is unknown. I don't know. someone please find out )
• Bit 12 is undefined. Always set to 0.
・ With bits 13 and 14, “P”, which is one of the input data for raster operation,
to select what to enter. When only bit 13 is 1, background
color is selected. When only bit 14 is 1, the foreground color is
selected. Foreground color when both bit 13 and bit 14 are 1
background color is selected. Both bit 13 and bit 14
When 0, the pattern register is selected.
Details of the foreground color and background color will be described later.
bit 14 13
0 0 pattern register
0 1 background color
1 0 foreground color
1 1 foreground and background colors
• Bit 15 is undefined. Always set to 0.
<<Mode register 1, I/O port 4A4H>>
• Bits 0 through 7 of this register define raster operations.
Raster operations have three inputs: "S", "P", and "D".
"P" is bits 13 and 14 of mode register 0;
"S" is set in bit 10 of this register, respectively;
“D” is data on VRAM.
Raster operations perform the following logical operations for each plane and each dot.
and writes the result to VRAM.
_
R = B7・S・D・P + B6・S・D・P +
_ _ _
B5・S・D・P + B4・S・D・P +
_ _ _
B3・S・D・P + B2・S・D・P +
_ _ _ _ _
B1・S・D・P + B0・S・D・P
_
…… NOT, + …… OR, ・ …… AND,
B0-B7 refer to bits 0 through 7 of this register.
Data that R writes to VRAM.
However, foreground color and background color are selected as P
If so:
R = B7・S・D・F + B6・S・D・F +
_ _ _
B5・S・D・F + B4・S・D・F +
_ _ _
B3・S・D・B + B2・S・D・B +
_ _ _ _ _
B1・S・D・B + B0・S・D・B
F is foreground color, B is background color.
• Bits 8 and 9 are settings related to changing the pattern register.
bit 9 8
0 0 Do not change the pattern register.
0 1 Load VRAM data when reading VRAM
1 0 VRAM data before writing at VRAM write
Load. However, with bits 11 and 12 of this register,
Select “P” as the data to be written to VRAM, and
Bits 13 and 14 of register 0 are set to “P” to
register, and the bits in this register
When 13 is set to 1, even if write access is made to VRAM,
The data read from the VRAM to the pattern register is
Since it is written to VRAM as it is, there is no meaning at all.
I don't.
However, loading data into the pattern register depends on the bits in this register.
13 works differently. That is, if bit 13 is 0, mode register
The pattern register for one plane set in bits 8 to 11 of star 0 is
Only change registers. If bit 13 is 1, all plane minutes
Load each plane's data into the pattern register.
• Bit 10 selects “S” for raster operations. If this bit is 1,
Data written to VRAM by the CPU is used for “S”. i.e. las
Data operations receive the address at which the CPU wrote the data to VRAM.
If this bit is 1, the written data is also treated as "S".
used for raster operations. If this bit is 0, the CPU is
data in VRAM at the address accessed by the CPU when reading from
When the CPU writes to VRAM with this as "S"
Used for raster operations.
From what I've tried so far, the older NEC EGCs don't have this behavior.
Bit 13 of this register must also be set to 1 when the bit is set to 1.
It doesn't seem to do any math. (Confirmed with VX) Please note this for compatibility
Please.
Also, when this bit is 1, NEC's EGC is explained at bit 13.
, one-plane read and compare read do not work properly.
• Bits 11 and 12 select the data to be written to VRAM.
When both bit 11 and bit 12 are 0, CPU data is written to 4 planes.
will be included. When only bit 11 is 1, raster for each plane, for each dot
- operation and write the result. When only bit 12 is 1, mode register
The “P” data determined by bits 13 and 14 of data 0 is written as is.
In any case the planes that are masked by the plane mask register are
Alternatively, dots masked by the dot mask register described later will not be changed.
plug. It is also affected by the setting of the shift mode register, which will be described later.
increase.
bit 12 11
0 0 CPU data
0 1 Result of raster operation
1 0 pattern register
• Bit 13 selects the data read when the CPU reads VRAM.
vinegar. If bit 13 is 0, one plane when the CPU reads from VRAM
The plane that is read and set by bits 8 to 11 of mode register 0
data is read as is. If bit 13 is 1, a compare read is performed.
will be Compare read is simply looking at VRAM data dot by dot.
Dots with the same color as the foreground color described below are sometimes treated as 1, and dots that are not
is read as 0. Actually, plain mask register
Only the plane set in the parameter is compared with the foreground color.
are not necessarily the same color.
However, for both one-plane read and compare read, this register bit
When 10 is 1, it doesn't work properly.
Also, as described above, the setting of this bit 13 changes the pattern register.
behavior is changed.
• Bits 14 and 15 are unused. Always set to 0.
<<Foreground color register, I/O port 4A6H>>
- Bits 0 to 3 set the foreground color as a 4-bit number.
set. If either bit 13 or bit 14 of mode register 0 is 1,
i.e. foreground color or background color as "P"
is not set, it cannot be changed. However, bit 1 of mode register 0
Even if both 3 and bit 14 are set to 0, the set value is saved, and the compare read
can be used at times.
• Bits 4 to 15 are unused. Always set to 0.
<<Dot mask register, I/O port 4A8H>>
This register indicates whether the contents of VRAM are changed or saved when writing data.
set for each dot.
Contrary to the plane mask register, this register
When a bit is 0, the color of the corresponding dot is preserved,
When the bit is 1, it is changed.
Correspondence between bits and dots is word access to VRAM (with EVEN, of course)
is the same as when in short,
from left
Bit 7 is the leftmost dot 1st
Bit 6 is the next dot to its right 2nd
:
:
Bit 0 is the 8th dot from the left 8th
Bit 15 is the dot to the right of it 9th
Bit 14 is the 10th dot to its right
:
:
Bit 9 is 2nd from right 15th
Bit 8 is the rightmost dot 16th
That's how we respond.
If both bits 13 and 14 of mode register 0 are set to 0,
You can't change it if you don't. Bit 13 or bit 14 of mode register 0
If either is set to 1, the setting will be saved and valid.
<<Background color register, I/O port 4AAH>>
• Bits 0 to 3 of background used as “P” for raster operations.
Sets the end color as a 4-bit number. Also foreground color
Either bit 13 or bit 14 of the mode register 0 is 1, i.e.
Either the foreground color or the background color is set as "P".
If it is not specified, it cannot be changed. However, bit 13 of mode register 0 and
Even if both bit 14 and bit 14 are set to 0, the set value is saved.
• Bits 4 to 15 are unused. Always set to 0.
<<Shift mode register, I/O port 4ACH>>
Bits 0 to 3 are the source dot address and bits 4 to 7 are the address.
Set each destination dot address as a 4-bit number.
vinegar. For details on the source bit address and destination bit address, see
I would like to explain it in § Actual raster operation (tentative name, under construction) §.
• Bit 12 sets the shift direction. 0 means right 1 means left
To do. For details, I would like to explain in § Actual raster operation (tentative name, under construction) §
is.
• Bits 8 to 11 and bits 13 to 15 are unused. always 0
to
<<Dot length register, I/O port 4AEH>>
Bits 0 to 11 set the dot length. one consecutive action
Sets how many dots to change (write) in set. dot to write
Sets the number -1 as a 12-bit number. Shift mode register bit
The number of dots differs depending on the setting of 12 (shift direction). detail
I would like to explain in § Actual Raster Operation (tentative name, under construction) §.
• Bits 12 to 15 are unused. Always set to 0.
╌╌╌╌╌╌╌╌╌╌╌ § § § VRAM read with EGC enabled § § § ╌╌╌╌╌╌╌╌╌╌╌╌╌
When EGC is enabled, there are two modes for reading VRAM: one-plane read and compare read. Once again, if this bit is 0, it will be one-plane read, and if it is 1, it will be compare read.
You can understand the one-plane read from the description of the register, so here, let's explain the compare read with a specific example.
Let's assume that VRAM contains the following data:
Contents of VRAM (per dot)
Dot 0 1 2 3 4 5 6 7 8 9 0AH 0BH 0CH 0DH 0EH 0FH
Color 0 1 2 3 4 5 6 7 8 9 0AH 0BH 0CH 0DH 0EH 0FH
Here, the numbers to the right of the “dot” are the remainders of dividing the dot's X coordinate by 16. Also, the quotients of dividing the X coordinates of 16 dots by 16 in this example are all the same. In other words, what I want to say is that these 16 dots are 16 points that can be read and written together by EVEN word access.
Showing the same data in plain form,
plane 0 = 05555H
Plane 1 = 03333H
Plane 2 = 00F0FH
Plane 3 = 0FF00H * In the format when the CPU accesses words
Since it is written, the upper and lower are reversed.
Then, if you change the plane mask register and foreground color and read access to the address containing the above data in VRAM, the data will be read as follows.
Plane Mask Register Foreground Color Read Value
(I/O port 4A0H) (I/O port 4A6H
bit 0 to bit 3)
0FFF0H 0 0080H
〃 1 0040H
〃 2 0020H
〃 3 0010H
〃 4 0008H
〃 5 0004H
〃 6 0002H
〃 7 0001H
〃 8 8000H
〃 9 4000H
〃 A 2000H
〃 B 1000H
〃 C 0800H
〃 D 0400H
〃 E 0200H
〃 F 0100H
0FFF1H 0 00C0H
〃 1 00C0H
〃 2 0030H
〃 3 0030H
〃 4 000CH
〃 5 000CH
〃 6 0003H
〃 7 0003H
〃 8 C000H
〃 9 C000H
〃 A 3000H
〃 B 3000H
〃 C 0C00H
〃 D 0C00H
〃 E 0300H
〃 F 0300H
0FFF6H 0 00AAH
〃 1 0055H
〃 2 00 AAH
〃 3 0055H
〃 4 00 AAH
〃 5 0055H
〃 6 00 AAH
〃 7 0055H
〃 8 AA00H
〃 9 5500H
〃 A AA00H
〃 B 5500H
〃 C AA00H
〃 D 5500H
〃 E AA00H
〃 F 5500H
╌╌╌╌╌╌╌╌╌╌╌ § § § Disable EGC § § § ╌╌╌╌╌╌╌╌╌╌╌╌
Disabling is the opposite of enabling.
EGC_OFFPROC
MOVAL,7
OUT6AH,AL
MOVAL,4
OUT6AH,AL
MOVAL,6
OUT6AH,AL
MOVAL,0
OUT7CH,AL
EGC_OFFENDP
Now you can disable EGC and return to normal state. No other steps are required.
Also, even if it is disabled once and then enabled again, the value of each EGC register is preserved. However, when GRCG is used, some EGC registers may change their values.
╌╌╌╌╌╌╌╌╌╌╌╌ § § § Relationship between EGC and GRCG § § § ╌╌╌╌╌╌╌╌╌╌╌╌
I wrote that some EGC registers change when GRCG is used, but let me explain a little about them.
《Mask register》
When GRCG is used in RMW mode, the value written to VRAM by the CPU is
written to the mask register.
For example, if the CPU writes 3EH to a byte with an even address, the mask register
will be 003EH. If you write 87H to a byte with an odd address,
The mask register value is 8700H. Also in the word of EVEN
When 9B61H is written, the value of the mask register becomes 9B61H, and ODD
Writing 530DH to a word results in 0053H.
《Foreground Color Register》
The foreground color register is set as one of 16 colors in EGC mode.
However, internally, it is expanded to 16 dots worth of data for the foreground
Think of it as writing to a docker register. I/O port 7EH
When writing to the GRCG tile register through the
The data is expanded to 16 dots by arranging two of them, and the foreground color is
written to the error register.
For example, if you write 000AH from I/O port 4A6H, foreground
The value inside the color register is
data 0=0000H,
Data 1=FFFFH,
Data 2 = 0000H, *Here, data n is
Data 3 = FFFFH Data corresponding to plane n.
becomes. Then, after writing the GRCG mode to I/O port 7CH,
When writing 82H, 5FH, A4H, and D9H in order from I/O port 7EH,
The internal value of the foreground color register is
data 0=8282H,
data 1=5F5FH,
Data 2=A4A4H, *Here, data n is
Data 3 = D9D9H Data corresponding to plane n.
becomes.
Also, the foreground color register is set to bit 13 of mode register 0
I wrote that it cannot be changed unless either 1 or 14 is 1, but GRCG mode
This does not apply to access from I/O port 7EH in . otherwise compatible
is no longer maintained.
╌╌╌╌╌╌╌╌╌╌╌╌ § § § NEC EGC, EPSON EGC § § § ╌╌╌╌╌╌╌╌╌╌╌╌
There are some differences between NEC's EGC and EPSON's EGC, and EPSON's EGC is higher compatible with NEC's EGC. Rather, I feel like it's a defect in NEC's EGC. I have already written here and there,
If bit 10 of mode register 1 is 1 at VRAM read, one play
Both unread and compare read do not work properly.
That's what it is. If you write the abnormal behavior uniformly,
The CPU performed a write access to the VRAM immediately before the read access
The data written by the CPU at that time is read.
That's how it is. With EPSON's EGC, even if bit 10 of mode register 1 is 1, one plane read and compare read can be performed normally. Set it to 0 and perform one-plane read and compare read.
●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●●
In creating this manual, "98 Super Technique", "98 Game Graphic",
Refer to the "PC-9801VX Hardware Manual" to independently check the operation.
did.
It's still incomplete, but I think it's good enough to be posted on the internet.
up. If you notice anything, please contact us.
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